搜索资源列表
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- 1位全加器的vhdl设计 通过两个半加起实现-A full adder of VHDL design increases since the adoption of two and a half to achieve
Electronic-Design-Automation-Vhdl
- 各种计数器，编码器，全加器等元件的VHDL语言描述-A variety of counters, encoders, such as full-adder components described in VHDL language
four_fadd
- 这是我在ISP编程实验中独立编写的采用结构化描述的四位全加器，通过四次映射一位全加器的方式实现了四位全加器的功能，并附有数码显示模块，将全加器的运算结果输出到数码管显示。-This is my ISP programming experiment in the preparation of an independent structural descr iption of the four full-adder, through the four mapping of a full adder
F_adder
- 这个源程序是关于全加器的，又需要的同学可以借鉴一下 -This source code is on the full adder, and also the needs of students can learn from you
shifter
- 完成一个加速器设计，全加器，具 8位计数器-Complete a accelerator design, full adder, an 8-bit counter
add_eight
- 用VHDL写的一个8位全加器的实验程序,供新手参考-Use VHDL to write an 8-bit full adder of the experimental procedures
binary_to_decima
- 8位全加器的VHDL描述，可用MAX+plusⅡ运行测试-8-bit full adder of the VHDL descr iption，MAX+ plus Ⅱ can be used to run test
fulladder
- 使用Vhdl语言实现数字电路全加器功能，算法比较简单，供初学者参考。-full adder
chap3
- 全加器和记数器的测试文件，可直接用于modsim测试-Full adder and counter test documents, can be used directly in testing modsim
FADDER_2
- 32位全加器 在querters II 下面运行成功 仿真 验证均已成功-32-bit full adder at querters II following the success of simulation runs have been successful
f__adder
- 全加器，半加器，或语句，三个建在一个文件中就可以用了-Full adder, half adder, or statement, three built in one file can be used
bitadder
- 一位全加器，VERILOG实现，包括测试文件，测试可用，欢迎下载，共同学习-A full adder, VERILOG implementation, including test papers, test available, please download, a common study
8WEIQUANJIAQI
- 8位全加器的VHDL语言描述，有需要的顶一下。-8-bit full adder described in the VHDL language, there is a need to click the top.
fadder
- 利用两个半加器来组成的全加器，是简单的vhdl语言入门-The use of two and a half adder to form the full adder is a simple entry-vhdl language
myf_adder
- 用例化语句和case语句编写的全加器的VHDL描述。-Of statements were prepared using the full adder of the VHDL descr iption.
afulladder
- 1位全加器 可以进行1位的二进制码的加法 想进行改进 改为4位或8位的全加器代码-A full adder can be an addition of the binary code would be changed to improve the 4 or 8-bit full adder code
w
- 用VHDL语言设计四位全加器，有低位进位和高位进位。-VHDL language with four full-adder design, there are low and the high binary binary.
fulladder
- 这是一个基于嵌入式的利用硬件高级描述语言编写的全加器程序，可以满足二进制全加的功能。-This is a use of embedded hardware-based high-level language to describe the All-Canadian program to meet the functions of the binary full adder.
full11adder
- this is a full adder using VHDL it s really helpful
quanjiaqi
- 4 级流水方式的8 位全加器-Way flow of 4 full adder 8. . . . . .